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lt3083 1 3083fa typical application description adjustable 3a single resistor low dropout regulator the lt ? 3083 is a 3a low dropout linear regulator that can be paralleled to increase output current or spread heat on surface mounted boards. architected as a precision current source and voltage follower, this new regulator fnds use in many applications requiring high current, adjustability to zero, and no heat sink. the device also brings out the collector of the pass transistor to allow low dropout opera - tiondown to 310mvwhen used with multiple supplies. a key feature of the lt3083 is the capability to supply a wide output voltage range. by using a reference current through a single resistor, the output voltage is programmed to any level between zero and 23v (dd-pak and to-220 packages). the lt3083 is stable with 10f of capacitance on the output, and the ic is stable with small ceramic ca - pacitors that do not require additional esr as is common with other regulators. internal protection circuitry includes current limiting and thermal limiting. the lt3083 is offered in the 16-lead tssop (with an exposed pad for better thermal character - istics), 12-lead 4mm 4mm dfn (also with an exposed pad), 5-lead to-220, and 5-lead surface mount dd-pak packages. l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. 1.5v to 0.9v at 3a supply (using 3.3v v control ) features applications n outputs may be paralleled for higher current and heat spreading n output current: 3a n single resistor programs output voltage n 50a set pin current: 1% initial accuracy n output adjustable to 0v n low output noise: 40v rms (10hz to 100khz) n wide input voltage range: 1.2v to 23v (dd-pak and to-220 packages) n low dropout voltage: 310mv n <1mv load regulation n <0.001%/v line regulation n minimum load current: 1ma n stable with minimum 10f ceramic capacitor n current limit with foldback and overtemperature protection n available in 16-lead tssop, 12-lead 4mm 4mm dfn, 5-lead to-220 and 5-lead surface mount dd-pak packages n high current all surface mount supply n high effciency linear regulator n post regulator for switching supplies n low parts count variable voltage supply n low output voltage power supplies set pin current distribution 49 51 3083 ta01b 49.5 50 50.5 set pin current distribution (a) n = 1052 3083 ta01a v control out in lt3083 set r min 909 * 10f 10f v out = 0.9v i max = 3a v in 1.5v 4.7f v control 3.3v r set 18.2k 1% 0.1f *optional for minimum 1ma load requirement
lt3083 2 3083fa absolute maximum ratings control pin voltage ............................................. 28v in pin voltage (t5, q packages) .................... 18v, C0.3v no overload or short-circuit ..................... 23v, C0.3v in pin voltage (df, fe packages) ..................... 8v, C0.3v no overload or short-circuit ..................... 14v, C0.3v set pin current (note 7) ..................................... 25ma set pin voltage (relative to out) .......................... 10v (note 1) all voltages relative to v out top view 13 out df package 12-lead (4mm 4mm) plastic dfn 12 11 8 9 10 4 5 3 2 1 in in in in v control v control out out out out out set 6 7 t jmax = 125c, ja = 37c/w, jc = 8c/w exposed pad (pin 13) is out, must be soldered to pcb fe package 16-lead plastic tssop 1 2 3 4 5 6 7 8 top view 16 15 14 13 12 11 10 9 out out out out out out set out out in in in in v control v control out 17 out t jmax = 125c, ja = 25c/w, jc = 8c/w exposed pad (pin 17) is out, must be soldered to pcb q package 5-lead plastic dd-pak tab is out front view in v control out set nc 5 4 3 2 1 t jmax = 125c, ja = 15c/w, jc = 3c/w t package 5-lead plastic to-220 in v control out set nc front view 5 4 3 2 1 tab is out t jmax = 125c, ja = 40c/w, jc = 3c/w pin configuration output short-circuit duration .......................... indefnite operating junction temperature range (notes 2, 10) e-, i-grades ........................................ C40c to 125c mp-grade ........................................... C55c to 125c storage temperature range .................. C65c to 150c lead temperature (soldering, 10 sec) t, q, fe packages only ..................................... 300c lead free finish tape and reel part marking* package description temperature range lt3083edf#pbf lt3083edf#trpbf 3083 12-lead (4mm 4mm) plastic dfn C40c to 125c lt3083efe#pbf lt3083efe#trpbf 3083fe 16-lead plastic tssop C40c to 125c lt3083eq#pbf lt3083eq#trpbf lt3083q 5-lead plastic dd-pak C40c to 125c lt3083et#pbf lt3083et#trpbf lt3083t 5-lead plastic to-220 C40c to 125c lt3083idf#pbf lt3083idf#trpbf 3083 12-lead (4mm 4mm) plastic dfn C40c to 125c lt3083ife#pbf lt3083ife#trpbf 3083fe 16-lead plastic tssop C40c to 125c order information
lt3083 3 3083fa order information lead free finish tape and reel part marking* package description temperature range lt3083iq#pbf lt3083iq#trpbf lt3083q 5-lead plastic dd-pak C40c to 125c lt3083it#pbf lt3083it#trpbf lt3083t 5-lead plastic to-220 C40c to 125c lt3083mpdf#pbf lt3083mpdf#trpbf 3083 12-lead (4mm 4mm) plastic dfn C55c to 125c lt3083mpfe#pbf lt3083mpfe#trpbf 3083fe 16-lead plastic tssop C55c to 125c lt3083mpq#pbf lt3083mpq#trpbf lt3083q 5-lead plastic dd-pak C55c to 125c lt3083mpt#pbf lt3083mpt#trpbf lt3083t 5-lead plastic to-220 C55c to 125c lead based finish tape and reel part marking* package description temperature range lt3083edf lt3083edf#tr 3083 12-lead (4mm 4mm) plastic dfn C40c to 125c lt3083efe lt3083efe#tr 3083fe 16-lead plastic tssop C40c to 125c lt3083eq lt3083eq#tr lt3083q 5-lead plastic dd-pak C40c to 125c lt3083et lt3083et#tr lt3083t 5-lead plastic to-220 C40c to 125c lt3083idf lt3083idf#tr 3083 12-lead (4mm 4mm) plastic dfn C40c to 125c lt3083ife lt3083ife#tr 3083fe 16-lead plastic tssop C40c to 125c lt3083iq lt3083iq#tr lt3083q 5-lead plastic dd-pak C40c to 125c lt3083it lt3083it#tr lt3083t 5-lead plastic to-220 C40c to 125c lt3083mpdf lt3083mpdf#tr 3083 12-lead (4mm 4mm) plastic dfn C55c to 125c lt3083mpfe lt3083mpfe#tr 3083fe 16-lead plastic tssop C55c to 125c lt3083mpq lt3083mpq#tr lt3083q 5-lead plastic dd-pak C55c to 125c lt3083mpt lt3083mpt#tr lt3083t 5-lead plastic to-220 C55c to 125c consult ltc marketing for parts specifed with wider operating temperature ranges. *the temperature grade is identifed by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifcations, go to: http://www.linear.com/tapeandreel/ the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c (note 2). electrical characteristics parameter conditions min typ max units set pin current i set v in = 1v, v control = 2v, i load = 1ma, t j = 25c v in 1v, v control 2v, 5ma i load 3a (note 9) l 49.5 49 50 50 50.5 51 a a output offset voltage (v out C v set ) v os v in = 1v, v control = 2v, i load = 1ma df, fe packages l C3 C4 0 0 3 4 mv mv t, q packages l C4 C6 0 0 4 6 mv mv load regulation (df, fe packages) ?i set ?v os ?i load = 1ma to 3a ?i load = 5ma to 3a (note 8) l C10 C0.4 C1 na mv load regulation (t, q packages) ?i set ?v os ?i load = 1ma to 3a ?i load = 5ma to 3a (note 8) l C10 C0.7 C4 na mv line regulation (df, fe packages) ?i set ?v os ?v in = 1v to 14v, ?v control = 2v to 25v, i load = 1ma ?v in = 1v to 14v, ?v control = 2v to 25v, i load = 1ma 0.1 0.002 0.01 na/v mv/v line regulation (t, q packages) ?i set ?v os ?v in = 1v to 23v, ?v control = 2v to 25v, i load = 1ma ?v in = 1v to 23v, ?v control = 2v to 25v, i load = 1ma 0.1 0.002 0.01 na/v mv/v minimum load current (notes 3, 9) v in = 1v, v control = 2v v in = 14v (df/fe) or 23v (t/q), v control = 25v l l 350 500 1 a ma
lt3083 4 3083fa the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c (note 2). electrical characteristics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: unless otherwise specifed, all voltages are with respect to v out. the lt3083 is tested and specifed under pulse load conditions such that t j ? t a . the lt3083e is 100% tested at t a = 25c. performance of the lt3083e over the full C40c to 125c operating junction temperature range is assured by design, characterization, and correlation with statistical process controls. the lt3083i regulators are guaranteed over the full C40c to 125c operating junction temperature range. the lt3083mp is 100% tested and guaranteed over the C55c to 125c operating junction temperature range. note 3: minimum load current is equivalent to the quiescent current of the part. since all quiescent and drive current is delivered to the output of the part, the minimum load current is the minimum current required to maintain regulation. note 4: for the lt3083, dropout is caused by either minimum control voltage (v control ) or minimum input voltage (v in ). both parameters are specifed with respect to the output voltage. the specifcations represent the minimum input-to-output differential voltage required to maintain regulation. note 5: the v control pin current is the drive current required for the output transistor. this current will track output current with roughly a 1:60 ratio. the minimum value is equal to the quiescent current of the device. note 6: output noise is lowered by adding a small capacitor across the voltage setting resistor. adding this capacitor bypasses the voltage setting resistor shot noise and reference current noise; output noise is then equal to error amplifer noise (see the applications information section). note 7: the set pin is clamped to the output with diodes through 1k resistors. these resistors and diodes will only carry current under transient overloads. note 8: load regulation is kelvin sensed at the package. note 9: current limit includes foldback protection circuitry. current limit decreases at higher input-to-output differential voltages. note 10: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed the maximum operating junction temperature when overtemperature protection is active. overtemperature protection (thermal limit) is typically active at junction temperatures of 165c. continuous operation above the specifed maximum operating junction temperature may impair device reliability. parameter conditions min typ max units v control dropout voltage (note 4) i load = 100ma i load = 1a i load = 3a l l 1.2 1.22 1.25 1.55 1.6 v v v v in dropout voltage (note 4) i load = 100ma l 10 25 mv i load = 1a, q, t packages i load = 1a, df, fe packages l l 120 90 190 160 mv mv i load = 3a, q, t packages i load = 3a, df, fe packages l l 310 240 510 420 mv mv v control pin current (note 5) i load = 100ma i load = 1a i load = 3a l l l 5.5 18 40 10 35 80 ma ma ma current limit v in = 5v, v control = 5v, v set = 0v, v out = C0.1v l 3 3.7 a error amplifer rms output noise (note 6) i load = 500ma, 10hz f 100khz, c out = 10f, c set = 0.1f 40 v rms reference current rms output noise (note 6) 10hz f 100khz 1 na rms ripple rejection v ripple = 0.5v p-p , i l = 0.1a, c set = 0.1f, c out = 10f f = 120hz f = 10khz f = 1mhz 85 75 20 db db db thermal regulation, i set 10ms pulse 0.003 %/w
lt3083 5 3083fa typical performance characteristics offset voltage distribution offset voltage (v out C v set ) offset voltage (v out C v set ) load regulation minimum load current dropout voltage, t/q packages (minimum in voltage) set pin current set pin current distribution ?50 set pin current (a) 49.6 49.7 50 150 3083 g01 49.5 49.8 49.9 50.5 50.4 50.3 50.2 50.1 50.0 25 ?25 0 75 100 125 temperature (c) offset voltage (v out C v set ) 0 offset voltage (mv) 5 25 3083 g05 ?1.00 ?0.75 ?0.50 1.00 0.75 0.50 0.25 0 ?0.25 10 15 20 input-to-output voltage (v) i load = 5ma 0 offset voltage (mv) 0.5 3 3083 g06 ?1.75 ?1.50 ?1.25 0.25 0 ?0.25 ?0.50 ?0.75 ?1.00 1 1.5 2.52 load current (a) t j = 25c t j = 125c ?50 change in offset voltage with load (mv) change in reference current with load (na) 50 150 3083 g07 ?1.6 ?1.4 0 ?0.2 ?0.6 ?0.8 ?1.0 ?1.2 25 ?25 0 75 100 125 temperature (c) ?0.4 ?300 ?250 100 50 ?50 ?100 ?150 ?200 0 change in reference current change in offset voltage (v out ? v set ) ?i load = 5ma to 3a v in = v control = v out + 2v ?50 minimum load current (ma) 50 150 3083 g08 0 0.2 1.4 1.2 1.0 0.8 0.6 0.4 25 ?25 0 75 100 125 temperature (c) v in, control ? v out = 1.5v v in,control ? v out = 23v v in = v control 0 minimum voltage (v in ? v out ) (mv) 0.5 3 3083 g09 0 50 100 400 350 300 250 200 150 1 1.5 2 2.5 load current (a) t j = 125c t j = 25c t j = ?50c t a = 25c, unless otherwise noted. 49 51 3083 g02 49.5 50 50.5 set pin current distribution (a) n = 1052 ?50 offset voltage (mv) 50 150 3083 g03 ?1.0 ?0.4 1.0 0.8 0.4 0.2 0 ?0.2 ?0.8 ?0.6 25 ?25 0 75 100 125 temperature (c) 0.6 i load = 5ma ?3 3 3083 g04 ?2 ?1 0 21 v os distribution (mv) n = 1052
lt3083 6 3083fa typical performance characteristics dropout voltage (minimum v control pin voltage) dropout voltage (minimum v control pin voltage) current limit current limit dropout voltage, fe/df packages dropout voltage, t/q packages (minimum in voltage) dropout voltage, fe/df packages (minimum in voltage) t a = 25c, unless otherwise noted. ?50 minimum v control pin voltage (v control ? v out ) (v) 50 150 3083 g14 0 1.6 1.2 0.8 1.4 1.0 0.6 0.4 0.2 25 ?25 0 75 100 125 temperature (c) i load = 3a 0 minimum voltage (v in ? v out ) (mv) 0.5 3 3083 g10 0 50 100 400 350 300 250 200 150 1 1.5 2 2.5 load current (a) t j = ?50c t j = 125c t j = 25c ?50 minimum in voltage (v in ? v out ) (mv) 50 150 3083 g11 0 100 500 400 300 450 350 250 200 150 50 25 ?25 0 75 100 125 temperature (c) i load = 100ma i load = 3a i load = 500ma i load = 1.5a ?50 minimum in voltage (v in ? v out ) (mv) 50 150 3083 g12 0 100 500 400 300 450 350 250 200 150 50 25 ?25 0 75 100 125 temperature (c) i load = 100ma i load = 500ma i load = 3a i load = 1.5a ?50 current limit (a) 50 150 3083 g15 0 5.0 3.0 2.0 4.5 2.5 4.0 3.5 1.5 1.0 0.5 25 ?25 0 75 100 125 temperature (c) v in = v control = 7v v out = 0v 0 current limit (a) 20 3083 g16 0 4.0 3.0 2.0 3.5 2.5 1.5 1.0 0.5 5 10 15 in-to-out differential (v in ? v out ) (v) t j = 25c 0 minimum v control pin voltage (v control ? v out ) (v) 0.5 3 3083 g13 0 0.2 0.4 1.6 1.4 1.2 1.0 0.8 0.6 1 1.5 2 2.5 load current (a) t j = 25c t j = 125c t j = ?50c
lt3083 7 3083fa typical performance characteristics v control pin current v control pin current residual output voltage with less than minimum load line transient response turn-on response turn-on response load transient response load transient response t a = 25c, unless otherwise noted. 0 load current (a) output voltage deviation (mv) 80 200 3083 g17 0 50 ?50 100 150 0 ?100 1.0 0.5 6020 40 140 160 100 120 180 time (s) v in = 2v v control = 3v v out = 1v c set = 0.1f ?i load = 100ma to 1a c out = 10f ceramic c out = 22f ceramic 0 in/ v control voltage (v) output voltage deviation (mv) 80 200 3083 g19 ?10 ?20 5 4 6 7 3 10 0 6020 40 140 160 100 120 180 time (s) v out = 1v i load = 10ma c out = 10f ceramic c set = 0.1f 0 in/ v control voltage (v) output voltage (v) 20 50 3083 g20 0 4 1 5 6 2 3 0 1.0 0.5 ?0.5 155 10 35 40 25 30 45 time (s) r set = 20k c set = 0 r load = 0.33 c out = 10f ceramic 0 in/ v control voltage (v) output voltage (v) 8 20 3083 g21 0 1 4 2 3 0 1.0 0.5 ?0.5 62 4 14 16 10 12 18 time (ms) r set = 20k c set = 0.1f r load = 1 c out = 10f ceramic 0 v control pin current (ma) 2 18 3083 g22 0 10 80 70 60 50 40 30 20 4 6 8 10 12 14 16 in-to-out differential (v in ? v out ) (v) i load = 3a i load = 1.5a device in current limit 0 load current (a) output voltage deviation (mv) 80 200 3083 g18 0 50 ?50 150 250 ?150 4 2 6020 40 140 160 100 120 180 time (s) ?i load = 500ma to 3a v in = 2v v control = 3v v out = 1v c set = 0.1f c out = 22f ceramic 0 v control pin current (ma) 0.5 3 3083 g23 0 10 70 60 50 40 30 20 1 1.5 2 2.5 load current (a) t j = ?50c t j = 125c t j = 25c v control ? v out = 2v v in ? v out = 1v 0 output voltage (mv) 2000 3083 g24 0 100 600 500 400 300 200 500 1000 1500 r set () r test v out set pin = 0v add 1n4148 for r test < 1k v in = 20v v in = 5v v in = 10v v in
lt3083 8 3083fa typical performance characteristics noise spectral density output voltage noise error amplifer gain and phase ripple rejection, single supply ripple rejection, dual supply, v control pin ripple rejection, dual supply, in pin 10 ripple rejection (db) 100 10m 3083 g25 0 10 100 70 60 90 80 50 40 30 20 1k 10k 100k 1m frequency (hz) i load = 0.1a i load = 1.5a c out = 10f ceramic c set = 0.1f ceramic ripple = 50mv p-p v in ? v control = v out(nominal) + 2v i load = 0.5a 10 ripple rejection (db) 100 10m 3083 g26 0 15 120 105 90 75 60 45 30 1k 10k 100k 1m frequency (hz) c out = 10f ceramic c set = 0.1f v in = v out(nominal) + 1v v control = v out(nominal) + 2v i load = 0.1a i load = 1.5a 10 ripple rejection (db) 100 10m 3083 g27 0 15 120 105 90 75 60 45 30 1k 10k 100k 1m frequency (hz) c out = 10f ceramic c set = 0.1f v in = v out(nominal) + 1v v control = v out(nominal) + 2v i load = 0.5a i load = 0.1a i load = 1.5a ?50 ripple rejectoin (db) 50 150 3083 g28 70 72 80 78 76 79 77 75 74 73 71 25 ?25 0 75 100 125 temperature (c) v in = v control = v out(nominal) + 2v ripple = 500mv p-p , ? = 120hz i load = 0.5a c set = 0.1f, c out = 10f ripple rejection (120hz) 10 error amplifier noise spectral density (nv/hz) reference current noise spectral density (pa/hz) 100 100k 3083 g29 10 1000 100 1 100 10 1k 10k frequency (hz) 3083 g30 v out 100v/div time 1ms/div v out = 1v, r set = 20k c set = 0.1f, c out = 10f i load = 3a 10 gain (db) 100 1m 3083 g31 ?15 ?12 21 12 9 18 15 6 3 0 ?6 ?3 ?9 ?396 ?360 36 ?108 ?144 0 ?36 ?72 ?180 ?216 ?288 ?252 ?324 1k 10k 100k frequency (hz) phase gain i load = 0.5a i load = 1.5a i load = 3a t a = 25c, unless otherwise noted.
lt3083 9 3083fa pin functions out (pins 1-5,13/pins 1-6,8,9,16,17/ pin 3, tab/ pin 3, tab): output. the exposed pad of the df package (pin 13) and the fe package (pin 17) and the tab of the dd-pak and to-220 packages is an electrical connection to out. connect the exposed pad of the df and fe packages and the tab of the dd-pak package directly to out on the pcb and the respective out pins for each package. there must be a minimum load current of 1ma or the output may not regulate. set (pin 6/pin 7/pin 2/pin 2): set point. this pin is the non-inverting input to the error amplifer and the regula - tion set point. a fxed current of 50a fows out of this pin through a single external resistor, which programs the output voltage of the device. output voltage range is zero to the v in(max) C v dropout . transient performance can be improved by adding a small capacitor from the set pin to ground. v control (pins 7,8/pins 10,11/pin 4/ pin 4): bias sup- ply. this is the supply pin for the control circuitry of the device. minimum input capacitance is 2.2f (see input capacitance and stability in the applications information section). the current fow into this pin is about 1.7% of the output current. for the device to regulate, this voltage must be more than 1.2v to 1.4v greater than the output voltage (see dropout specifcations in the electrical char - acteristics section). in (pins 9-12/pins 12-15/pin 5/pin 5): power input. this is the collector to the power device of the lt3083. the output load current is supplied through this pin. minimum in capacitance is 10f (see input capacitance and stabil - ity in applications information section). for the device to regulate, the voltage at this pin must be more than 0.1v to 0.5v greater than the output voltage (see dropout specifcations in the electrical characteristics section). nc (na/na/pin 1/pin 1): no connection. no connect pins have no connection to internal circuitry and may be tied to v in , v control , v out , gnd, or foated. (df/fe/q/t packages) block diagram ? + v control in 50a 3083 bd out set
lt3083 10 3083fa applications information the lt3083 regulator is easy to use and has all the protection features expected in high performance regulators. included are short-circuit protection and safe operating area protec - tion, as well as thermal shutdown with hysteresis. the lt3083 fts well in applications needing multiple rails. this new architecture adjusts down to zero with a single resistor, handling modern low voltage digital ics as well as allowing easy parallel operation and thermal management without heat sinks. adjusting to zero output allows shutting off the powered circuitry. when the input is pre-regulated, such as with a 5v or 3.3v input supply, external resistors can help spread the heat. a precision 0 tc 50a reference current source connects to the noninverting input of a power operational amplifer. the power operational amplifer provides a low impedance buffered output to the voltage on the noninverting input. a single resistor from the noninverting input to ground sets the output voltage. if this resistor is set to 0?, zero output voltage results. therefore, any output voltage can be obtained between zero and the maximum defned by the input power supply. the beneft of using a true internal current source as the reference, as opposed to a bootstrapped reference in older regulators, is not so obvious in this architecture. a true reference current source allows the regulator to have gain and frequency response independent of the impedance on the positive input. on older adjustable regulators, such as the lt1086, loop gain changes with output voltage and bandwidth changes if the adjustment pin is bypassed to ground. for the lt3083, the loop gain is unchanged with output voltage changes or bypassing. output regulation is not a fxed percentage of output voltage, but is a fxed fraction of millivolts. use of a true current source allows all of the gain in the buffer amplifer to provide regulation, and none of that gain is needed to amplify up the reference to a higher output voltage. the lt3083 has the collector of the output transistor con - nected to a separate pin from the control input. since the dropout on the collector (in pin) is typically only 310mv, two supplies can be used to power the lt3083 to reduce dissipation: a higher voltage supply for the control circuitry and a lower voltage supply for the collector. this increases effciency and reduces dissipation. to further spread the heat, a resistor inserted in series with the collector moves some of the heat out of the ic to spread it on the pc board (see the section reducing power dissipation ). the lt3083 can be operated in two modes. three termi - nal mode has the v control pin connected to the in pin and gives a limitation of 1.25v dropout. alternatively, the v control pin is separately tied to a higher voltage and the in pin to a lower voltage giving 310mv dropout on the in pin, minimizing total power dissipation. this allows for a 3a supply regulating from 2.5v in to 1.8v out or 1.8v in to 1.2v out with low power dissipation. programming output voltage the lt3083 sources a 50a reference current that fows out of the set pin. connecting a resistor from set to ground generates a voltage that becomes the reference point for the error amplifer (see figure 1). the refer - ence voltage equals 50a multiplied by the value of the set pin resistor. any voltage can be generated and there is no minimum output voltage for the regulator. figure 1. basic adjustable regulator + ? lt3083 in v control v control out 3083 f01 set c out r set v out c set + v in + 50a v out = 50a ? r set
lt3083 11 3083fa applications information table 1 lists many common output voltages and the clos - est standard 1% resistor values used to generate that output voltage. regulation of the output voltage requires a minimum load current of 1ma. for a true zero voltage output operation, return this 1ma load current to a negative supply voltage. table 1. 1% resistors for common output voltages v out (v) r set (k) 1 20 1.2 24.3 1.5 30.1 1.8 35.7 2.5 49.9 3.3 66.5 5 100 with the lower level current used to generate the refer - ence voltage, leakage paths to or from the set pin can create errors in the reference and output voltages. high quality insulation should be used (e.g., tefon, kel-f); cleaning of all insulating surfaces to remove fuxes and other residues will probably be required. surface coating may be necessary to provide a moisture barrier in high humidity environments. minimize board leakage by encircling the set pin and circuitry with a guard ring operated at a potential close to itself. tie the guard ring to the out pin. guard rings on both sides of the circuit board are required. bulk leak - age reduction depends on the guard ring width. 50na of leakage into or out of the set pin and its associated circuitry creates a 0.1% reference voltage error. leakages of this magnitude, coupled with other sources of leakage, can cause signifcant offset voltage and reference drift, especially over the possible operating temperature range. figure 2 depicts an example of a guard ring layout. if guard ring techniques are used, this bootstraps any stray capacitance at the set pin. since the set pin is a high impedance node, unwanted signals may couple into the set pin and cause erratic behavior. this will be most noticeable when operating with minimum output capacitors at full load current. the easiest way to remedy this is to bypass the set pin with a small amount of capacitance from set to ground, 10pf to 20pf is suffcient. stability and input capacitance typical minimum input capacitance is 10f for in and 2.2f for v control . these amounts of capacitance work well using low esr ceramic capacitors when placed close to the lt3083 and the circuit is located in close proximity to the power source. higher values of input capacitance may be necessary to maintain stability depending on the application. oscillating regulator circuits are often viewed as a problem of phase margin and inadequate stability with the output capacitor used. more and more frequently, the problem is not the regulator operating without suffcient output capacitance, but instead with too little input capacitance. the entire circuit must be analyzed and debugged as a whole; conditions relating to the input of the regulator cannot be ignored. the lt3083 input presents a high impedance to its power source: the output voltage and load current are independent of input voltage variations. to maintain stability of the regulator circuit as a whole, the lt3083 must be powered from a low impedance supply. when using short supply lines or powering directly from a large switching supply, there is no issuehundreds or thousands of microfarads of capacitance are available through a low impedance. figure 2. guard ring layout example for df package 3083 f02 set pin gnd out
lt3083 12 3083fa applications information when longer supply lines, flters, current sense resistors, or other impedances exist between the supply and the input to the lt3083, input bypassing should be reviewed if stability concerns are seen. just as output capacitance supplies the instantaneous changes in load current for output transients until the regulator is able to respond, input capacitance supplies local power to the regulator until the main supply responds. when impedance separates the lt3083 from its main supply, the local input can droop so that the output follows. the entire circuit may break into oscillations, usually characterized by larger amplitude oscillations on the input and coupling to the output. low esr, ceramic input bypass capacitors are acceptable for applications without long input leads. however, applica - tions connecting a power supply to an lt3083 circuits in and gnd pins with long input wires combined with low esr, ceramic input capacitors are prone to voltage spikes, reliability concerns and application-specifc board oscil- lations. the input wire inductance found in many battery powered applications, combined with the low esr ceramic input capacitor, forms a high-q lc resonant tank circuit. in some instances this resonant frequency beats against the output current dependent ldo bandwidth and interferes with proper operation. simple circuit modifcations/solu - tions are then required. this behavior is not indicative of lt3083 instability, but is a common ceramic input bypass capacitor application issue. the self-inductance, or isolated inductance, of a wire is directly proportional to its length. wire diameter is not a major factor on its self-inductance. for example, the self- inductance of a 2-awg isolated wire (diameter = 0.26") is about half the self-inductance of a 30-awg wire (diameter = 0.01"). one foot of 30-awg wire has about 465nh of self-inductance. one of two ways reduces a wires self-inductance. one method divides the current fowing towards the lt3083 between two parallel conductors. in this case, the farther apart the wires are from each other, the more the self-in - ductance is reduced; up to a 50% reduction when placed a few inches apart. splitting the wires basically connects two equal inductors in parallel, but placing them in close proximity gives the wires mutual inductance adding to the self-inductance. the second and most effective way to reduce overall inductance is to place both forward and return current conductors (the input and gnd wires) in very close proximity. two 30-awg wires separated by only 0.02", used as forward- and return- current conductors, reduce the overall self-inductance to approximately one- ffth that of a single isolated wire. if wiring modifcations are not permissible for the applica - tions, including series resistance between the power supply and the input of the lt3083 also stabilizes the application. as little as 0.1? to 0.5?, often less, is effective in damping the lc resonance. if the added impedance between the power supply and the input is unacceptable, adding esr to the input capacitor also provides the necessary damping of the lc resonance. however, the required esr is generally higher than the series impedance required. stability and output capacitance the lt3083 requires an output capacitor for stability. it is designed to be stable with most low esr capacitors (typically ceramic, tantalum or low esr electrolytic). a minimum output capacitor of 10f with an esr of 0.5 or less is recommended to prevent oscillations. larger values of output capacitance decrease peak deviations and provide improved transient response for larger load current changes. bypass capacitors, used to decouple individual components powered by the lt3083, increase the effective output capacitor value. for improvement in transient performance, place a capacitor across the volt - age setting resistor. capacitors up to 1f can be used. this bypass capacitor reduces system noise as well, but start-up time is proportional to the time constant of the voltage setting resistor (r set in figure 1) and set pin bypass capacitor. give extra consideration to the use of ceramic capacitors. ceramic capacitors are manufactured with a variety of di - electrics, each with different behavior across temperature and applied voltage. the most common dielectrics used are specifed with eia temperature characteristic codes of z5u, y5v, x5r and x7r. the z5u and y5v dielectrics are good for providing high capacitances in a small package, but they tend to have strong voltage and temperature coeffcients as shown in figures 3 and 4. when used with a 5v regulator, a 16v 10f y5v capacitor can exhibit an
lt3083 13 3083fa applications information figure 5. parallel devices effective value as low as 1f to 2f for the dc bias voltage applied and over the operating temperature range. the x5r and x7r dielectrics result in more stable characteristics and are more suitable for use as the output capacitor. the x7r type has better stability across temperature, while the x5r is less expensive and is available in higher values. care still must be exercised when using x5r and x7r capacitors. the x5r and x7r codes only specify operating temperature range and maximum capacitance change over temperature. capacitance change due to dc bias with x5r and x7r capacitors is better than y5v and z5u capacitors, but can still be signifcant enough to drop capacitor values below appropriate levels. capacitor dc bias characteristics tend to improve as component case size increases, but expected capacitance at operating voltage should be verifed. voltage and temperature coeffcients are not the only sources of problems. some ceramic capacitors have a piezoelectric response. a piezoelectric device generates voltage across its terminals due to mechanical stress. in a ceramic capacitor, the stress can be induced by vibrations in the system or thermal transients. paralleling devices higher output current is obtained by paralleling multiple lt3083s together. tie the individual set pins together and tie the individual in pins together. connect the outputs in common using small pieces of pc trace as ballast resistors to promote equal current sharing. pc trace resistance in m/inch is shown in table 2. ballasting requires only a tiny area on the pcb. table 2. pc board trace resistance weight (oz) 10mil width 20mil width 1 54.3 27.1 2 27.1 13.6 trace resistance is measured in m?/in the worst-case room temperature offset, only 4mv (dd-pak, t packages) between the set pin and the out pin, allows the use of very small ballast resistors. as shown in figure 5, each lt3083 has a small 10m? ballast resistor, which at full output current gives better than 80% equalized sharing of the current. the external figure 3. ceramic capacitor dc bias characteristics figure 4. ceramic capacitor temperature characteristics dc bias voltage (v) change in value (%) 3083 f03 20 0 ?20 ?40 ?60 ?80 ?100 0 4 8 10 2 6 12 14 x5r y5v 16 both capacitors are 16v, 1210 case size, 10f temperature (c) ?50 40 20 0 ?20 ?40 ?60 ?80 ?100 25 75 3083 f04 ?25 0 50 100 125 y5v change in value (%) x5r both capacitors are 16v, 1210 case size, 10f + ? lt3083 v in v control out set 10m + ? lt3083 v in v in 4.8v to 20v v out 3.3v 6a v control out 10f 10f set 33k 3083 f05 10m
lt3083 14 3083fa applications information resistance of 10m? (5m? for the two devices in paral - lel) only adds about 30mv of output regulation drop at an output of 6a. with an output voltage of 3.3v, this only adds 1% to the regulation. of course, paralleling more than two lt3083s yields even higher output current. spreading the devices on the pc board also spreads the heat. series input resistors can further spread the heat if the input-to-output difference is high. quieting the noise the lt3083 offers numerous noise performance advan - tages. every linear regulator has its sources of noise. in general, a linear regulators critical noise source is the reference. in addition, consider the error amplifers noise contribution along with the resistor dividers noise gain. many traditional low noise regulators bond out the voltage reference to an external pin (usually through a large value resistor) to allow for bypassing and noise reduction. the lt3083 does not use a traditional voltage reference like other linear regulators. instead, it uses a 50a reference current. the 50a current source generates noise current levels of 3.16pa/ hz (1na rms ) over the 10hz to 100khz bandwidth). the equivalent voltage noise equals the rms noise current multiplied by the resistor value. the set pin resistor generates spot noise equal to 4ktr (k = boltzmanns constant, 1.38 ? 10 C23 j/k, and t is abso- lute temperature) which is rms summed with the voltage noise. if the application requires lower noise performance, bypass the voltage setting resistor with a capacitor to gnd. note that this noise-reduction capacitor increases start-up time as a factor of the rc time constant. the lt3083 uses a unity-gain follower from the set pin to the out pin. therefore, multiple possibilities exist (besides a set pin resistor) to set output voltage. for example, using a high accuracy voltage reference from set to gnd removes the errors in output voltage due to reference current tolerance and resistor tolerance. active driving of the set pin is acceptable. the typical noise scenario for a linear regulator is that the output voltage setting resistor divider gains up the noise reference, especially if v out is much greater than v ref . the lt3083s noise advantage is that the unity gain follower presents no noise gain whatsoever from the set pin to the output. thus, noise fgures do not increase accordingly. error amplifer noise is typically 126.5nv/ hz (40v rms ) over the 10hz to 100khz bandwidth). the error amplifers noise is rms summed with the other noise terms to give a fnal noise fgure for the regulator. curves in the typical performance characteristics sec- tion show noise spectral density and peak-to-peak noise characteristics for both the reference current and error amplifer over the 10hz to 100khz bandwidth. load regulation the lt3083 is a foating device. no ground pin exists on the packages. thus, the ic delivers all quiescent current and drive current to the load. therefore, it is not possible to provide true remote load sensing. the connection resis - tance between the regulator and the load determines load regulation performance. the data sheets load regulation specifcation is kelvin sensed at the packages pins. nega - tive-side sensing is a true kelvin connection by returning the bottom of the voltage setting resistor to the negative side of the load (see figure 6). connected as shown, system load regulation is the sum of the lt3083s load regulation and the parasitic line resistance multiplied by the output current. to minimize load regulation, keep the positive connection between the regulator and load as short as possible. if possible, use large diameter wire or wide pc board traces. + ? lt3083 in v control out 3080 f06 set r set r p parasitic resistance r p r p load figure 6. connections for best load regulation
lt3083 15 3083fa applications information thermal considerations the lt3083s internal power and thermal limiting circuitry protects itself under overload conditions. for continuous normal load conditions, do not exceed the 125c maximum junction temperature. carefully consider all sources of thermal resistance from junction-to-ambient. this includes (but is not limited to) junction-to-case, case-to-heat sink interface, heat sink resistance or circuit board-to-ambient as the application dictates. consider all additional, adjacent heat generating sources in proximity on the pcb. surface mount packages provide the necessary heat sinking by using the heat spreading capabilities of the pc board, copper traces, and planes. surface mount heat sinks, plated through-holes and solder-flled vias can also spread the heat generated by power devices. junction-to-case thermal resistance is specifed from the ic junction to the bottom of the case directly, or the bottom of the pin most directly in the heat path. this is the lowest thermal resistance path for heat fow. only proper device mounting ensures the best possible thermal fow from this area of the packages to the heat sinking material. note that the exposed pad of the dfn and tssop pack - ages and the tab of the dd-pak and to-220 packages are electrically connected to the output (v out ). tables 3 through 5 list thermal resistance as a function of copper areas on a fxed board size. all measurements were taken in still air on a 4-layer fr-4 board with 1oz solid internal planes and 2oz external trace planes with a total fnished board thickness of 1.6mm. layers are not connected electrically or thermally. table 3. df package, 12-lead dfn copper area board area thermal resistance (junction-to-ambient) topside* backside 2500mm 2 2500mm 2 2500mm 2 18c/w 1000mm 2 2500mm 2 2500mm 2 22c/w 225mm 2 2500mm 2 2500mm 2 29c/w 100mm 2 2500mm 2 2500mm 2 35c/w *device is mounted on topside. table 4. fe package, 16-lead tssop copper area board area thermal resistance (junction-to-ambient) topside* backside 2500mm 2 2500mm 2 2500mm 2 16c/w 1000mm 2 2500mm 2 2500mm 2 20c/w 225mm 2 2500mm 2 2500mm 2 26c/w 100mm 2 2500mm 2 2500mm 2 32c/w *device is mounted on topside. table 5. q package, 5-lead dd-pak copper area board area thermal resistance (junction-to-ambient) topside* backside 2500mm 2 2500mm 2 2500mm 2 13c/w 1000mm 2 2500mm 2 2500mm 2 14c/w 125mm 2 2500mm 2 2500mm 2 16c/w *device is mounted on topside. t package, 5-lead to-220 thermal resistance (junction-to-case) = 3c/w for further information on thermal resistance and using thermal information, refer to jedec standard jesd51, notably jesd51-12. pcb layers, copper weight, board layout and thermal vias affect the resultant thermal resistance. tables 3 through 5 provide thermal resistance numbers for best-case 4-layer boards with 1oz internal and 2oz external copper. modern, multilayer pcbs may not be able to achieve quite the same level performance as found in these tables. calculating junction temperature example: given an output voltage of 0.9v, a v control voltage of 3.3v 10%, an in voltage of 1.5v 5%, output current range from 10ma to 3a and a maximum ambient temperature of 50c, what will the maximum junction temperature be for the dd-pak on a 2500mm 2 board with topside copper of 1000mm 2 ?
lt3083 16 3083fa applications information the power in the drive circuit equals: p drive = (v control C v out )(i control ) where i control is equal to i out /60. i control is a function of output current. a curve of i control vs i out can be found in the typical performance characteristics curves. the total power equals: p total = p drive + p output the current delivered to the set pin is negligible and can be ignored. v control(max_continuous) = 3.630v (3.3v + 10%) v in(max_continuous) = 1.575v (1.5v + 5%) v out = 0.9v, i out = 3a, t a = 50c power dissipation under these conditions is equal to: p drive = (v control C v out )(i control ) i control = i out 60 = 3a 60 = 50ma p drive = (3.630v C 0.9v)(50ma) = 137mw p output = (v in C v out )(i out ) p output = (1.575v C 0.9v)(3a) = 2.03w total power dissipation = 2.16w junction temperature will be equal to: t j = t a + p total ? ja (using tables) t j = 50c + 2.16w ? 16c/w = 84.6c in this case, the junction temperature is below the maxi - mum rating, ensuring reliable operation. reducing power dissipation in some applications it may be necessary to reduce the power dissipation in the lt3083 package without sacrifc - ing output current capability. two techniques are available. the frst technique, illustrated in figure 7, employs a resistor in series with the regulators input. the voltage drop across rs decreases the lt3083s input-to-output differential voltage and correspondingly decreases the lt3083s power dissipation. as an example, assume: v in = v control = 5v, v out = 3.3v and i out(max) = 2a. use the formulas from the calculating junction temperature section previously discussed. without series resistor r s , power dissipation in the lt3083 equals: p total = 5v ? 3.3v ( ) ? 2a 60 ? ? ? ? ? ? + 5v ? 3.3v ( ) ? 2a = 3.46w if the voltage differential (v diff ) across the npn pass transistor is chosen as 0.5v, then rs equals: r s = 5v ? 3.3v ? 0.5v 2a = 0.6 ? power dissipation in the lt3083 now equals: p total = 5v ? 3.3v ( ) ? 2a 60 ? ? ? ? ? ? + 0.5v ? 2a = 1.06w the lt3083s power dissipation is now only 30% compared to no series resistor. r s dissipates 2.4w of power. choose appropriate wattage resistors or use multiple resistors in parallel to handle and dissipate the power properly. figure 7. reducing power dissipation using a series resistor + ? lt3083 in v control out v out v in v in c2 3083 f07 set r set r s c1
lt3083 17 3083fa + ? lt3083 in v control out v out v in c2 3083 f08 set r set r p c1 figure 8. reducing power dissipation using a parallel resistor the second technique for reducing power dissipation, shown in figure 8, uses a resistor in parallel with the lt3083. this resistor provides a parallel path for current fow, reducing the current fowing through the lt3083. this technique works well if input voltage is reasonably constant and output load current changes are small. this technique also increases the maximum available output current at the expense of minimum load requirements. as an example, assume: v in = v control = 5v, v in(max) = 5.5v, v out = 3.3v, v out(min) = 3.2v, i out(max) = 2a and i out(min) = 0.7a. also, assuming that r p carries no more than 90% of i out(min) = 630ma. calculating r p yields: r p = 5.5v ? 3.2v 0.63a = 3.65 ? (5% standard value = 3.6?) the maximum total power dissipation is (5.5v C 3.2v) ? 2a = 4.6w. however, the lt3083 supplies only: 2a ? 5.5v ? 3.2v 3.6 ? = 1.36a therefore, the lt3083s power dissipation is only: p diss = (5.5v C 3.2v) ? 1.36a = 3.13w r p dissipates 1.47w of power. as with the frst technique, choose appropriate wattage resistors to handle and dis - sipate the power properly. with this confguration, the lt3083 supplies only 1.36a. therefore, load current can increase by 1.64a to a total output current of 3.64a while keeping the lt3083 in its normal operating range. applications information
lt3083 18 3083fa typical applications + ? lt3083 in v in v control out v out 3083 ta02 set r1 on off shutdown q1 vn2222ll q2* vn2222ll q2 insures zero output in the absence of any output load. * adding shutdown current source low dropout voltage led driver dac-controlled regulator + ? lt3083 in 1a d1 v control out v in 3083 ta04 set r1 20k r2 1 c1 + ? lt3083 in v control out 10f v in 3083 ta05 set 450k v out + ? 150k 150k lt1991 gain = 4 spi ltc2641 + ? lt3083 in v control out 0.33 20k 3083 ta03 set i out 0a to 3a 10f v in 10v 10f
lt3083 19 3083fa adding soft-start coincident tracking lab supply typical applications + ? lt3083 in v control out 10f v out3 5v set c3 10f + ? lt3083 in v control out v out2 3.3v 3083 ta06 set r2 16.2k 34k c2 10f c1 10f + ? lt3083 in v control v in 7v to 20v out set r1 49.9k v out1 2.5v + ? lt3083 in v in 4.8v to 20v v control out v out 3.3v 3a c out 10f 3083 ta07 set r1 66.5k c2 0.01f c1 10f d1 1n4148 + ? lt3083 + ? lt3083 in in v in 12v to 18v v control v control out out 10f 100f v out 0v to 10v 3083 ta08 set set + 15f r4 200k 0.33 20k 0a to 3a + 15f +
lt3083 20 3083fa typical applications high voltage regulator ramp generator reference buffer boosting fixed output regulators + ? lt3083 6.1v in 1n4148 v in 50v v control out v out 3a v out = 20v v out = 50a ? r set 3083 ta09 set r set 402k 10f 15f 10f buz11 10k + + + ? lt3083 in v in 5v v control out v out 3083 ta10 set vn2222ll vn2222ll 10f 10f 10nf + ? lt3083 in v in v control out v out * 3083 ta11 set output input c1 1f gnd c2 10f lt1019 *min load 0.5ma 3083 ta12 10m 20m 42* 47f 3.3v out 4.5a v control 33k *4mv drop ensures lt3083 is off with no load multiple lt3083?s can be used + ? lt3083 10f 5v out set in lt1963-3.3
lt3083 21 3083fa low voltage, high current adjustable high effciency regulator* typical applications 2.7v to 5.5v ? 2 100f 2.2meg 100k 470pf 10k 1000pf 2 100f 294k 12.1k 0.47h 78.7k 100k 124k pv in sw 2n3906 sv in i th r t v fb sync/mode pgood run/ss sgnd pgnd ltc3610 + ? lt3083 in v control out set + ? lt3083 in v control out 0v to 4v ? 12a set + ? lt3083 in v control out set 3083 ta13 + ? lt3083 in v control out 100f set + + + *differential voltage on lt3083 is 0.6v set by the v be of the 2n3906 pnp. 10m 10m 10m 10m ? maximum output voltage is 1.5v below input voltage
lt3083 22 3083fa adjustable high effciency regulator* 2 terminal current source typical applications 3083 ta14 4.5v to 25v ? 10f 100k 0.1f 68f 4.7h b340a 10k 10k 15.4k 1f 0.47f tp0610l 63.4k 600khz + ? lt3083 in v control out set 4.7f 0v to 10v ? 3a *differential voltage on lt3083 1.4v set by the tpo610l p-channel threshold. 200k ? maximum output voltage is 2v below input voltage 680pf v in boost sw fb run/ss v control rt bd gnd lt3680 200k 3083 ta15 r1 20k + ? lt3083 c comp * in v control set *c comp r1 10 10f r1 10 2.2f i out = 1v r1
lt3083 23 3083fa package description fe package 16-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1663 rev h) exposed pad variation bb fe16 (bb) tssop rev g 0910 0.09 ? 0.20 (.0035 ? .0079) 0 ? 8 0.25 ref 0.50 ? 0.75 (.020 ? .030) 4.30 ? 4.50* (.169 ? .177) 1 3 4 5 6 7 8 10 9 4.90 ? 5.10* (.193 ? .201) 16 1514 13 12 11 1.10 (.0433) max 0.05 ? 0.15 (.002 ? .006) 0.65 (.0256) bsc 2.94 (.116) 0.195 ? 0.30 (.0077 ? .0118) typ 2 recommended solder pad layout 0.45 0.05 0.65 bsc 4.50 0.10 6.60 0.10 1.05 0.10 2.94 (.116) 3.58 (.141) 3.58 (.141) millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc fe package 16-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1663 rev h) exposed pad variation bb
lt3083 24 3083fa package description df package 12-lead plastic dfn (4mm 4mm) (reference ltc dwg # 05-08-1733 rev ?) 4.00 0.10 (4 sides) note: 1. drawing is proposed to be made a jedec package outline mo-220 variation (wggd-x)?to be approved 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 1 6 12 7 bottom view?exposed pad 2.65 0.10 0.75 0.05 r = 0.115 typ 0.25 0.05 0.50 bsc 2.50 ref 3.38 0.10 0.200 ref 0.00 ? 0.05 (df12) dfn 0806 rev ? recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 0.25 0.05 0.50 bsc 3.10 0.05 4.50 0.05 package outline pin 1 notch r = 0.20 typ or 0.35 45 chamfer 2.65 0.05 3.38 0.05 2.50 ref
lt3083 25 3083fa package description q package 5-lead plastic dd-pak (reference ltc dwg # 05-08-1461 rev e) q(dd5) 0610 rev e .028 ? .038 (0.711 ? 0.965) typ .143 +.012 ?.020 ( ) 3.632 +0.305 ?0.508 .067 (1.702) bsc .013 ? .023 (0.330 ? 0.584) .095 ? .115 (2.413 ? 2.921) .004 +.008 ?.004 ( ) 0.102 +0.203 ?0.102 .050 .012 (1.270 0.305) .059 (1.499) typ .045 ? .055 (1.143 ? 1.397) .165 ? .180 (4.191 ? 4.572) .330 ? .370 (8.382 ? 9.398) .060 (1.524) typ .390 ? .415 (9.906 ? 10.541) 15 typ .420 .350 .585 .090 .042 .067 recommended solder pad layout .325 .205 .080 .585 .090 recommended solder pad layout for thicker solder paste applications .042 .067 .420 .276 .320 note: 1. dimensions in inch/(millimeter) 2. drawing not to scale .300 (7.620) .075 (1.905) .183 (4.648) .060 (1.524) .060 (1.524) .256 (6.502) bottom view of dd pak hatched area is solder plated copper heat sink q package 5-lead plastic dd pak (reference ltc dwg # 05-08-1461 rev e)
lt3083 26 3083fa package description t package 5-lead plastic to-220 (standard) (reference ltc dwg # 05-08-1421) t5 (to-220) 0801 .028 ? .038 (0.711 ? 0.965) .067 (1.70) .135 ? .165 (3.429 ? 4.191) .700 ? .728 (17.78 ? 18.491) .045 ? .055 (1.143 ? 1.397) .095 ? .115 (2.413 ? 2.921) .013 ? .023 (0.330 ? 0.584) .620 (15.75) typ .155 ? .195* (3.937 ? 4.953) .152 ? .202 (3.861 ? 5.131) .260 ? .320 (6.60 ? 8.13) .165 ? .180 (4.191 ? 4.572) .147 ? .155 (3.734 ? 3.937) dia .390 ? .415 (9.906 ? 10.541) .330 ? .370 (8.382 ? 9.398) .460 ? .500 (11.684 ? 12.700) .570 ? .620 (14.478 ? 15.748) .230 ? .270 (5.842 ? 6.858) bsc seating plane * measured at the seating plane
lt3083 27 3083fa information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 4/11 revised part markings in order information section 3
lt3083 28 3083fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com linear technology corporation 2011 lt 0411 rev a ? printed in usa related parts typical application paralleling regulators + ? lt3083 in v in 4.8v to 28v v control out 10m v out 3.3v 6a 3083 ta16 33.2k set 22f 10f + ? lt3083 in v control out 10m set part number description comments lt1185 3a negative low dropout regulator v in : C4.5v to C35v, 0.8v dropout voltage, dd-pak and to-220 packages lt1764/ lt1764a 3a, fast transient response, low noise ldo 340mv dropout voltage, low noise: 40v rms , v in = 2.7v to 20v, to-220 and dd packages. a version stable also with ceramic capacitors lt1963/a 1.5a low noise, fast transient response ldo 340mv dropout voltage, low noise: 40v rms , v in = 2.5v to 20v, a version stable with ceramic capacitors, to-220, dd, sot-223 and so-8 packages lt1965 1.1a, low noise, low dropout linear regulator 290mv dropout voltage, low noise: 40v rms , v in : 1.8v to 20v, v out : 1.2v to 19.5v, stable with ceramic capacitors, to-220, dd-pak, msop and 3mm 3mm dfn packages lt3022 1a, low voltage, vldo linear regulator v in : 0.9v to 10v, dropout voltage: 145mv typical, adjustable output (v ref = v out(min) = 200mv), stable with low esr, ceramic output capacitors, 16-pin dfn (5mm 3mm) and 16-lead msop packages lt3070 5a, low noise, programmable v out , 85mv dropout linear regulator with digital margining dropout voltage: 85mv, digitally programmable v out : 0.8v to 1.8v, digital output margining: 1%, 3% or 5%, low output noise: 25v rms (10hz to 100khz), parallelable: use two for a 10a output, stable with low esr ceramic output capacitors (15f minimum), 28-lead 4mm 5mm qfn package lt3071 5a, low noise, programmable vout, 85mv dropout linear regulator with analog margining dropout voltage: 85mv, digitally programmable v out : 0.8v to 1.8v, analog margining: 10%, low output noise: 25v rms (10hz to 100khz), parallelable: use two for a 10a output, i mon output current monitor, stable with low esr ceramic output capacitors (15f minimum), 28-lead 4mm 5mm qfn package lt3080/ lt3080-1 1.1a, parallelable, low noise, low dropout linear regulator 300mv dropout voltage (2-supply operation), low noise: 40v rms , v in : 1.2v to 36v, v out : 0v to 35.7v, current-based reference with 1-resistor v out set; directly parallelable (no op amp required), stable with ceramic capacitors, to-220, dd-pak, sot-223, ms8e and 3mm 3mm dfn-8 packages; -1 version has integrated internal ballast resistor lt3082 200ma, parallelable, single resistor, low dropout linear regulator outputs may be paralleled for higher output, current or heat spreading, wide input voltage range: 1.2v to 40v, low value input/output capacitors required: 0.22f, single resistor sets output voltage, 8-lead sot-23, 3-lead sot-223 and 8-lead 3mm 3mm dfn packages lt3085 500ma, parallelable, low noise, low dropout linear regulator 275mv dropout voltage (2-supply operation), low noise: 40v rms , v in : 1.2v to 36v, v out : 0v to 35.7v, current-based reference with 1-resistor v out set; directly parallelable (no op amp required), stable with ceramic capacitors, ms8e and 2mm 3mm dfn-6 packages ltc3026 1.5a, low input voltage vldo linear regulator v in : 1.14v to 3.5v (boost enabled), 1.14v to 5.5v (with external 5v), v do = 0.1v, i q = 950a, stable with 10f ceramic capacitors, 10-lead msop-e and dfn-10 packages

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